The present application claims the benefit of U.S. Provisional Patent Application Nos. 60/399,635 entitled “Data Dispersion and Mirroring Method with Fast Dual Erasure Correction and Multi-Dimensional Capabilities” filed on Jul. 29, 2002 and 60/460,545 entitled “Composite Data Protection Method for Micro Level Data” filed Apr. 4, 2003.
To information theorists the field of Error Control Codes and Coding was developed to utilize redundancy to maximize transmission rates. To the engineer it is useful to use redundancy to improve data resiliency, guarantee data integrity and to construct fail-safe hardware designs. Some codes are useful only for the detection of errors. Error correction codes are designed to recognize when data is in error, then locate the errors and finally remove the errors and if possible leave some degree of assurance that the final result is accurate. A third major category is that of erasure recovery codes. This is the case where segments of data are dispersed with the expectation that not all segments will be retrievable. Error control codes have been developed for all three major categories; error detection, error correction and erasure recovery. Sometimes a code can be used for double or triple duty. A common practice is to not use all of the mathematical robustness for correction but leave some for post correction data integrity verification. In other instances it is necessary to nest two or more different codes in order to accomplish multiple requirements to an acceptable degree.
Different forms of error control coding have been developed to handle the error modes inherent to ever changing communications channels, memory systems, storage networks and devices and system networks. Within hardware systems error modes are caused by transient effects such as alpha particles, others by asperities in storage media, by electrical noise and signal skew, by physical wear or chemical alteration, by inter-symbol interference and many other phenomena. Each may affect data differently and occur at a different rate and distribution pattern. This has spawned a continuous evolution of new codes and decoding techniques.
Specific examples of error detection codes are the Cyclic Redundancy Check codes CRC-16, CRC-320 and CCITT. They are popular codes used to detect errors in relatively short messages. Their capabilities are well understood but limited. A common application of CRC codes is in data communication where data is formatted into small sequential packets with each packet protected by a CRC checkword. As packets are input at the receiving node the CRC is recalculated and compared with the received CRC checkword. A good compare may result in the return of an acknowledge (ACK) signal. A miss compare might result in an Automatic Retry Request (ARQ) negative acknowledge (NACK) signal. After a limited number of retries the algorithm might assume that success is not likely and the transmission is terminated, delayed or rerouted. In specific applications that can tolerate inaccurate data the data can simply be flagged as being in error.
In coding theory the minimum difference in binary bit assignments between any two codewords is referred to as the Hamming distance, d. There is a direct correlation between the minimum Hamming distance of a code and its' ability to distinguish one codeword from another and also a code's potential for detecting and correcting random bits in error.
Consider the CCITT 16-bit polynomial code. The generator polynomial is g(x)=1+x5 +x12+x16. It has a Hamming distance d=4 giving it the following capabilities: 1) It can detect all combinations of 3 random bit errors over its length of 65,536 bits, d=t+1; 2) It can detect all odd bit errors; and 3) It can detect all burst errors of up to 16 bits length.
Single and multiple bit correction over short to medium length messages often use Hamming and BCH codes. This would include applications such as computer memories and other devices that exhibit transient single bit error modes.
Special codes have been developed to correct for single and multiple short burst errors over medium data lengths. Fire codes and the Kasami Computer Generated Cyclic codes are common single burst codes. Reed-Solomon codes are a popular multiple burst error correcting code type. Primary applications for burst error codes are disk read errors due to media asperities or scratches and inter-symbol electronic interference.
In 1967 a code was developed by Nordstrom and Robinson as an existence proof of an n=15, k=8, d=5 code since an n=12, k=5, d=5 code had already been discovered. Here n=total code bits and k=information bits. With a Hamming distance of d=5 it would detect up to 4 single bit errors and correct up to 2 single bit errors. The code length of 15 would be cumbersome in the 8-bit world. It was later determined that the N–R code could be extended to an n=16, k=8 code.
In the book Algebraic Coding Theory, (Elwyn Belekamp 1968) the author published that the polynomial whose roots are the finite field elements of order p is called the cyclotomic polynomial, denoted by Q(P) (x). He noted that the factors of Q(17) (x) are gl(x)=1+x3+x4+x5+x8 and g2(x)=1+x+x2+x4+x6+x7+x8 and that each polynomial could correct two random errors in a block of 17 binary digits.
U.S. Pat. No. 3,868,632 (Hong et al.) discloses that the Q(17) (x) code factors can be further exploited as an erasure code for 9 track tapes called Optimal Rectangular Code. Both tape and tape heads exhibit wear due to contact recording and the aggressive abuse of tape by the handling mechanisms. The most common associated error mode is loss of a media track on tape or the temporary or catastrophic loss of a read/write head. The erasure decoder was designed to recover data on the fly for up to two (typically outside edges) simultaneously failing data streams. The code is actually two different codes working in tandem plus a pointer system to identify which two of nine channels have failed or likely to be in error. Data is formatted in 7-byte groups, each a 56-bit rectangular data array with an 8-bit ECC and 8 bits of side-band parity. A similar dual erasure method has been designed for disk arrays.
The paper, A Case for Redundant Array of Inexpensive Disk (RAID), (Patterson et al., University of California—Berkeley, 1987) describes several methods for achieving disk device resiliency. RAID-1 mirroring is the simple process of generating and maintaining a single duplicate copy of a file, device or file system. RAID-2 has roots with Hamming single error correction/double error detection (SECDED) codes used primarily for computer memory systems. Two forms of erasure recovery that have roots with tape data track erasure recovery are RAID-3 and RAID-5, an extension of RAID-3. Also pertinent to this discussion is RAID-6. RAID-6 is a method that tolerates two device failures (erasures) and also has roots with dual erasure tape systems. There are also RAID-6 examples based on multiple level parity calculations across small data arrays.
The commodity nature of disk storage devices keeps driving the costs lower and lower with a tendency toward producing a single commodity product that supports the smallest to the largest applications. The increasing data capacity of storage products and the business and legal responsibilities now make data resiliency and data integrity requirements more essential than ever before. Business continuity back-up recovery performance requirements often dictate disk drives over tape. This is an opportunity to raise the reliability, integrity and resiliency of those and other applications via the use of new error control coding techniques. RAID-6 dual erasure capability is necessary for data protection while the first failure is being repaired.
Considerable work is in progress in the area of error coding for mobile communications. Convolution codes and many computer generated forward error correcting codes have been developed for serial transmission in the presence of errors. Many different kinds of array codes are being constructed and tested. Some of these rely on a composite of multiple error codes and innovative forms of ARQ retry algorithms for satisfying bandwidth and integrity requirements. In comparison they are exceedingly complex and require complex decoding algorithms such as the Viterbi and turbo methods.
A critical component of contemporary processor and storage architectures is the fabric of switches, routers and links used to scale processors, storage devices and network connectivity. These networks carry different data formats but in general move small to medium size packets of processor cache lines or communication and storage data packets. The requirement for resiliency and data integrity is high. To date cost has limited the error control measures to CRC error detection with ARQ retry methods and rerouting when alternate paths exist. There is inadequate end-to-end data integrity validation and hardware resiliency. Here too it is necessary and possible to raise the integrity, reliability and resiliency of data systems via new error control coding techniques.
The prior art includes some solutions based on the dispersal of data with the recovery via dual erasure control coding. In the context of small disk arrays this is commonly referred to as method RAID level 6. The number of disk drives clustered in these arrays typically varies from as few as four to six to as many as nine or seventeen. Other erasure control applications may be called information dispersal and reconstruction, erasure or loss resilient coding or in specific context forward error correction coding, FEC.
U.S. Pat. Nos. 5,128,810 (Halford) and 5,283,791 (Halford), in the name of the present inventor, show dual drive error correction method using a data bit dispersal with erasure control technique. This method requires a parity side-band drive and a significant amount of computation due to the dual dependent ECC codes (odd parity and irreducible polynomial). This approach is relatively cumbersome and slow if implemented in software. Also the code data array is rectangular M * (M-1) which limits data size flexibility.
U.S. Pat. No. 5,485,474 (Rabin), shows a method also significantly computationally intensive that suggests using a vector processor, systolic array or parallel processor for decoding. Therefore the encoding and decoding is both slow or relatively expensive to implement. Original data is not transmitted in clear systematic form. The preferred embodiment works with multiple bytes per codeword which results in file size matching issues, magnifies the size of encode/decode mechanisms and when dealing with application data can be a source of error migration during both the encode and decode processes. It also does not provide simultaneous error detection and correction nor a multi-dimensional data recovery capability.
U.S. Pat. No. 5,271,012 (Blaum et al.) describes an M*(M−1) data array where M is a prime number. Pairs of simple parity bits are recursively encoded over data in respective and recursive diagonal and row order array directions. The example embodiment shows a 5-drive array with data on 3 drives and parity on 2 drives. Data is encoded in 12-bit quanta and dispersed across the 5 drives in 4-bit quanta.
U.S. Pat. No. 5,579,475 (Blaum et al.) is a continuation of the 1993 patent with certain specific improvements such as a less recursive parity calculation algorithm. The array size M is again a prime number. While the operations are not mathematically complex the calculations are numerous.
U.S. Pat. No. 6,088,330 (Bruck et al.) and U.S. Pat. No. 6,128,277(Bruck et al.) describes a data array encoding where the array is N*N square and N preferably a prime number. If data is dispersed via columns, parity is developed in rows causing each dispersal element to contain both data and parity. Two separate independent parity row calculations are made along two slopes within the data array then stacked at the bottom to complete the encoding. The encoding supports specific error correction capabilities along with dual column erasure recovery. The 5×5 array described in the preferred embodiment represents 15 data bits and 10 parity bits. The decoding operations are numerous.
U.S. Pat. No. 6,138,125 (DeMoss) describes yet another dual-parity method that also requires the formatting of data into arrays with parity diagonals. Here the array is also a square N*N where N+1 is a prime number. Parity positions are the major diagonals and data positions are the remaining non-comer diagonal locations. The computation uses simple logical exclusive-or operations but the algorithm described is relatively extensive, as are all others that format data around diagonal parity vectors.
Many contemporary systems are being built by creating a network of processor/memory nodes utilizing single chip processors designed to meet the basic requirements for systems ranging from workstations to high-end supercomputers. Systems fabrics can be created by the interconnection of routers or switches together with a combination of processor nodes, I/O ports and fabric interconnect ports. An important aspect of some of these systems is for nodes, links and routers to have a specific degree of resiliency. Those with a more automatic resiliency capability are referred to as being fail-safe, self-healing or autonomic. This requirement is also emerging into storage network subsystems.